The present invention relates to a lock detection system for detection of whether for example a phase or frequency locked loop has caught lock. The lock detection system being for use in high speed communication systems.
In high speed communication systems, it is upon transmission and/or reception of digital data signals normally required to synchronise the transmitted data bits with a clock signal. Normally, it is necessary to provide a reference clock signal to the transmission circuit, for example by providing an external reference clock signal to the transmission circuit where after the reference clock signal is synchronised, such as phase or frequency locked, to the data signal before sampling of the data signal with the synchronised clock signal.
To verify whether the system has caught lock or not, i.e. whether the clock and data signals are synchronised, a frequency difference between for example a controlled oscillator of the transmission circuit and the reference clock may be detected whereby information of whether the clock and data signals are synchronised, i.e. whether the data signal and the clock signal have caught lock, is provided. Alternatively, the controlled oscillator may be aligned to the reference clock or swept continuously.
To avoid the need for providing an external clock to the system, the present invention relates in a first aspect to a lock detection method for generating a lock signal, the method comprising the steps of providing a data signal and a clock signal to a lock detection unit, the data signal being describable by an eye pattern, the data signal and the clock signal being in lock when a data transition occurs in the center of a first transition period, the lock detection unit comprising: detection of absence or presence of a data transition of the data signal in a first partial period centered around the center of the first transition period and generating a first output signal having a first logic value in response to the presence of a data transition and having a second logic value in response to the absence of a data transition in the first partial period, detection of absence or presence of a data transition of the data signal in a second partial period centered around the center of the eye and generating a second output signal having a first logic value in response to the absence of a data transition and having a second logic value in response to the presence of a data transition in the second partial period, and comparing the first and second output signals and generating a lock signal according to the comparison.
According to a second aspect of the present invention a lock detection system for generating a lock signal is provided, the system comprising a phase or frequency locked loop providing a data signal and a clock signal, the data signal being describable by an eye pattern, the data signal and the clock signal being in lock when a data transition occurs in the center of a first transition period, a lock detection unit for detection of absence or presence of a data transition of the data signal in a first partial period centered around the center of the first transition period and generating a first output signal having a first logic value in response to the presence of a data transition and having a second logic value in response to the absence of a data transition in the first partial period, detection of absence or presence of a data transition of the data signal in a second partial period centered around the center of the eye and generating a second output signal having a first logic value in response to the absence of a data transition and having a second logic value in response to the presence of a data transition in the second partial period, and comparing means for comparing the first and second output signals and generating a lock signal according to the comparison.
The eye pattern is a pattern defined as the synchronized superposition of all possible realizations of the data signal viewed within a particular signalling interval. The data signal is thus capable of being described by an eye pattern, so as to provide an evaluation of the overall system performance including effects of receiver noise, intersymbol interference, etc. Typically, the eye pattern has an eye opening which may be termed the eye opening period where only a few transitions occurs and a transition period wherein the majority of transitions occurs. When the clock signal and the data signal are in lock, the transitions will preferably occur substantially in the center of the transition period and the period wherein the transitions occur are termed a xe2x80x98first partial periodxe2x80x99, the first partial period being centered around the center of the transition period, whereas there will be no transitions in the center of the eye opening period and the period wherein there are substantially no transitions are termed a xe2x80x98second partial periodxe2x80x99, the second partial period being centered around the center of the eye opening period. If, for example, the length of the period of the data signal is T, the length of the first and the second partial periods may be T/2.
The data signal and the clock signal may be provided to the lock detection unit from a phase or frequency locked loop. The phase or frequency locked loop may comprise a phase or frequency detector, such as a bang bang phase detector and a controlled oscillator, preferably a voltage controlled oscillator. The lock detection system may further comprise a sweep generator adapted to sweep the voltage applied to the voltage controlled oscillator of the phase or frequency locked loop. The sweep generator is enabled when the lock detection signal is set, and the phase or frequency locked loop is hereby able to catch lock again.
Preferably, the lock detection unit comprises a bang bang phase detector. Furthermore, the lock detection unit may comprise a delay circuit adapted to shift the phase of the incoming clock signal received from the phase or frequency locked loop substantially 90xc2x0 in relation to the incoming clock signal. If, for example, the period of the data signal is T, the delay circuit may be adapted to delay the incoming clock signal by xc2xc of the period, i.e. xc2xc T.
The lock signal may be provided to any comparing means for comparing the first and second output signals. The comparing means may, for example, count the number of data transitions in the first and the second partial period, and on the basis of the number of transitions in the first and the second partial period, respectively, determine whether the system has caught lock or not. If, for example, the number of data transitions in the first partial period is substantially equal to the number of data transitions in the second partial period, the data transitions are randomly distributed and, hence, the system is out of lock, so that the lock signal is set thereby triggering the sweep generator. Correspondingly, if the number of data transitions in the first partial period is substantially larger than the number of data transitions in the second partial period, indicating that the data transitions occur in the center of the transition period so that the clock signal and the data signal are synchronised, no enabling signal will be set.
The comparing means may, thus, comprise a counter, the first and the second output signals being provided to the counter so that when there is transmission in the first partial period, a valid state, the counter will be incremented, whereas a transmission in the second period, a non valid state, will decrement the counter. When the system is in lock, the counter will run off. Otherwise, the counter will not run off in a prescribed time interval and the lock signal will be set and the sweep generator enabled.
The comparing means may for example comprise a charge pump. The first and the second output signals may thus be provided to the charge pump, and when a transmission has been detected in the first partial period, a valid state, the charge pump will be charged and correspondingly, the charge pump will be discharged when a transmission in the second partial period, a non-valid state, has occurred. The charge pump may for example be discharged through a leakage current. When the charge pump voltage then decreases to below a pre-set reference voltage indicating that the number of data transitions in the first partial period is not substantially larger than the number of data transitions in the second partial period, the lock signal will be set and the sweep generator may be enabled.